1. Field of the Invention
The present invention relates generally to the logical partitioning of a shared memory structure of a computer system. More particularly, the present invention is directed towards logical partitioning a cache memory between computer domains.
2. Description of Background Art
Multinode computer networks are often partitioned into domains, with each domain functioning as an independent machine with its own address space. An operating system runs separately on each domain. Partitioning permits the resources of a computer network to be efficiently allocated to different tasks, to provide flexibility in the use of a computer system, and to provide isolation between computer resources to limit the effects of hardware or software faults in one part of the network from interfering with the operation of the entire system.
FIG. 1 shows an illustration of a multimode computer system including central processing unit (CPU) nodes 105, memory nodes 110, and input/output (I/O) nodes 115 coupled to a system interconnect 120. Partition definition registers (not shown in FIG. 1), may be used to partition the multimode system into domains 130, 135, 140.
Conventionally, each domain has its own memory structures. This can be implemented as one or more local cache memories 145 which are kept coherent via a sparse directory 147 for each domain. FIG. 2A illustrates a conventional addressing technique for addressing a memory structure within a domain. A cache memory 200 is a data array for storing sets 205 of data. Each set 205 is also sometimes described in the art as a data line. In a traditional cache memory structure, each cache line entry 202 stored in the cache typically has an associated tag field 206. The value of the index 207 of the address indicates to which set 205 of the cache the address maps to.
In a K-way set associative cache, each set (cache address) consists of a set of K-lines of data entries, with each data entry in the set having its own tag field 206. When a new word is brought into the cache the tag bits are stored along with the data bits. When a CPU generates a memory request, the index 207 of the memory address is used to select a set 205 in the cache, i.e., a set 205 in the cache is indexed by the portion of the memory address called the index 207. The tag 210 of the CPU memory address is compared with the tag 206 of an entry 202 from the cache. If the tags 206 and 210 match there is a hit and the desired word entry is in the cache. For a K-way set associative cache, each of the K-lines in a set has its own tag and the tags for each entry are compared in parallel with the incoming address with a hit occurring if one of the tags match. Interleaving may be included so that multiple independent requests may be processed. Consequently, an interleave field 215 identifies which leaf to use. An offset field 220 identifies which data structure with the cache line is being accessed. FIG. 2B illustrates a conventional hardware system having comparators and multiplexors to output a signal indicative of a hit if the tag portion of the address matches the tag of an entry that is being addressed.
It will be understood that FIG. 2A represents a generalized addressing system that includes a variety of special memory structures. For example, the cache memory does not have to be interleaved (Y=0). If the cache memory structure does not use tags (W=0), the cache acts like a random access memory (RAM) in that every access is a hit. Moreover, if the cache memory structure does not have an index (X=0) it acts as a fully associative memory or a Content Addressible Memory (CAM).
A drawback of computer system 100 is that changes in domain partitioning and usage patterns may result in inefficient use of the memory hardware. Referring again to FIG. 1, in a typical computer system the domain partitioning of the system may change over time to meet new needs, i.e., the computer system may be configured to change the number of domains to meet new needs. However, since each domain requires at least one cache memory structure the total number of cache memories must be selected to be at least equal to a maximum number of domains for which computer system 100 is designed to support. If the number of domains is less than the maximum value there will be one or more idle memories. This is inefficient in regards to the use of cache memory hardware.
Therefore, there is a need for a system and method of improving the allocation of memory structures in partitioned computer systems.
A system and method of logically partitioning a cache memory between computer domains using an extended memory address is disclosed. The extended memory address includes an address space identifier for extending a conventional memory address with at least one bit uniquely identifying the address space of a domain from which a data request is made to the cache memory. In one embodiment the address space identifier has tag extension bits and index extension bits that are used to extend the tag bits and index bits of a conventional memory address. In this embodiment, a data set in the cache memory is accessed by an index value that includes the index bits and the index extension bits and a hit is determined from a tag value that includes the tag bits and the tag extension bits.